 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| ame, inc. 1 ame9001 ccfl backlight controller l small package: 24 pin qsop l drives multiple tubes l automatically checks for common fault conditions l 7.0v < vbatt < 24v l low component count l low idd < 3.5ma l <1ua shutdown mode the ame9001 controller provides a cost efficient means to drive single or multiple cold cathode fluorescent lamps (ccfl). specifically the ame9001 drives 3 external mosfets that, in turn, drive a wirewound transformer that is coupled to the ccfl. the ame9001 includes features such as soft start, duty cycle dimming control, and fault detection. it is designed to work with input voltages from 7v up to 24v. when disabled the circuit goes into a zero current mode. for applications that use a piezoelectric transformer please look at the ame9000. l notebook computers l lcd/tft displays n general description n features n applications n pin configuration ame9001 24pin qsop 1. vref 2. ce 3. ssc 4. rdelta 5. faultb 6. rt2 7. vss 8. ovp 9. cs 10.cscomp 11.csdet 12.nc 13. outc 14. outapb 15. outa 16. vbatt 17. vdd1 18. vdd 19. ct1 20. fb 21. comp 22. bright 23. ssv 24. pnp 1 2 3 4 5 6 7 8 9 10 24 23 22 21 20 19 18 17 16 15 11 12 14 13 ame9001 ame 9001 controller external components ccfl array n + resistors + capacitors light n system block diagram
ame, inc. 2 ccfl backlight controller ame9001 n pin description pin # pin name pin description 1vref reference. compensation point for the 3.4v internal voltage reference. must have bypass capacitor connected here to vss. 2ce chip enable. when low (<0.4v) the chip is put into a low current (~0ua) shutdown mode. 3 ssc blanking interval ramp. during the first cycle this pin sources 1 m a. during subsequent cycles it sources 150 m a. this is primarily used to provide a "blanking interval" at the beginning of every dimming cycle to temporarily disable the fault protection circuitry. (see application notes.) 4 rdelta a resistor connected from this pin to vbatt modulates the switching frequency as a function of battery voltage. 5faultb0.1 m f cap to vss. 6rt2 a resistor from this pin to vss sets the minimum frequency of the vco. the voltage at this pin is 1.5v 7 vss negative supply. connect to system ground. 8ovp over voltage protection input. indirectly senses the voltage at the secondary of the transformer through a resistor (or capacitor) divider. it will immediately turn the circuit off if the voltage at ovp is over 3v. it will also turn the chip off if the voltage at ovp is less than 250mv for 4 successive clock cycles after the vo l t a g e at ssc has risen above 3v ( ssc>3v ) . 9cs negative input of the auxiliary error amplifier(ea2). in this application it is normally shorted to cscomp 10 cscomp output of the auxiliary error amplifier(ea2). in this application the auxiliary error amp is in a unity gain configuration and the voltage at cscomp =1.25v as long as ssc > 1.25v. otherwise cscomp is clamped to the voltage at ssc. 11 csdet current sense detect. connect this pin to the ccfl current sense resistor divider. if this pin is below 250mv for 4 consecutive clock cycles after ssc > 3v then the circuit will shutdown. 12 nc must float. 13 outc drives one of the external nfets, opposite phase of outapb. 14 outapb drives one of the external nfets, opposite phase of outc. 15 outa drives the high side pfet. 16 vbatt battery input. this is the positive supply for the outa driver. 17 vdd1 must be tied to vdd. 18 vdd regulated 5v supply input. 19 ct1 sets the dimming cycle freq uency. usually about 100hz. 20 fb negative input of the voltage control loop error amplifier. 21 comp output of the voltage control loop error amplifier. 22 bright brightness control input. a dc voltage on this controls the duty cycle of the dimming cycle. this pin is compared to a 3v ramp at the ct1 pin. 23 ssv soft start ramp for the voltage control loop. (20ua source current.) 24 pnp drives the base of an external pnp transistor used for the 5v ldo. ame, inc. 3 ame9001 ccfl backlight controller n ordering information " xxxxxxxx hn " for internal code n absolute maximum ratings n recommended operating conditions n thermal information caution: stress above the listed absolute maximum rating may cause permanent damage to the device part number marking output voltage package operating temp. range AME9001AETH AME9001AETH xxxxxxxxhn yyww n/a qsop-24 - 40 o c to + 85 o c parameter maximum unit battery voltage (vbatt) 25 v esd classification b parameter rating unit battery voltage (vbatt) 7 - 24 v ambient temperature range - 40 to + 85 o c junction temperature - 40 to + 125 o c maximum unit 325 o c / w 150 o c 300 o c thermal resistance (qsop - 24) maximum junction temperature parameter maximum lead temperature (10 sec) ame, inc. 4 ccfl backlight controller ame9001 parameter symbol min typ max units output voltage v dd 4.9 5.15 5.35 v line regulation v ddline -0.5 0.5 % load regulation v ddload -0.2 0.2 % temperature drift v ddtc 0.5 % initial voltage v ref 3.25 3.4 3.525 v line regulation v refline -0.1 0.1 % temperature drift v reftc 100 ppm/c ramp amplitude v ct1 3v frequency f ct1 70 130 hz line regulation line ct1 -0.5 0.5 % temperature drift tc ct1 =+-3 % comparator offset vos ct1 10 mv initial frequency f vco(outa) 47 52 khz line regulation line vco -0.8 0.8 % temperature drift tc vco +-0.5 % vco pullin range pull vco rt2/(rdelta x 5) % offset voltage, wrt vref v os -40 40 mv input bias current i b 1na input offset current i os 1na open loop gain a ol 70 db unity gain frequency f t 1mhz output high voltage (comp) v oh 3.39 v output low voltage v ol 0.4 v output high voltage (cscomp) v oh 4.77 v i source = 50ua i sink = 500ua 7< vbatt < 24v -10c < ta < 70c i source = 50ua error amplifiers (fb, comp, cs, cscomp) -10c < ta < 70c 7< vbatt < 24v rt2 = 56k vco oscillator (rt2, rdelta) test condition brightness oscillator (ct1, bright) 7 ame, inc. 6 ccfl backlight controller ame9001 n block diagram figure 1. ame9001 block diagram 9 10 11 12 16 15 14 13 1 1 2 2 3 3 4 4 21 22 23 24 5 6 7 8 20 19 18 17 c2 1uf c3 22nf r2 56k q3-1 q2 d4 r10 604 d5 c7 4.7uf c4 0.01uf c8 47nf q1 r4 2k outc outapb outa vbatt vdd1 vdd ct1 fb comp bright ssv pnp vref ce ssc rdelta faultb rt2 vss ovp cs cscomp csdet nc 7 - 24v c5 10uf to brightness control voltage to chip enable logic r7 30k d6 t1 q3-2 1.25v 2.5v - + - + - + clamp1 -+ - + f_range f_min vco_control ramp clk vco 0 3.4v reference 150ua 1ua ea1 ea2 r3 1.2meg vbatt r9 249 r35 r34 5.0v ldo pnp vref vddok first ovp ssc vddok chop norm clk csdet ce fault logic pwm 1 chop 2 outa outapb outc 5 6 7 duty 0 output driver slow ramp gen. c14 1000pf c31 0.1 m f ame, inc. 7 ame9001 ccfl backlight controller n application schematic figure 2. single tube application schematic (7v < vbatt < 24v) (note, ovp is disabled in this drawing) bill of materials c7 4.7 uf q1 2n3906 r6 51k bright r4 2k battery c4 0.01uf q3 irf7341 c8 47nf r7 30.1k c2 1uf ce c3 22nf r1 1meg s1 c6 0.1uf q2 si3457dv t1 out + r12 5k r11 5k d4 out - r10 604 r9 249 r20 100k r2 49.9 k vref 1 ce 2 ssc 3 rdelta 4 fault 5 rt2 6 vss 7 ovp 8 cs 9 cscomp 10 csdet 11 nc 12 outc 13 outapb 14 outa 15 vbatt 16 vdd1 17 vdd 18 ct1 19 fb 20 comp 21 bright 22 ssv 23 pnp 24 ame9001 c1 0.1uf r3 1.2 meg r13 10k c5 10uf vss d5 d6 d3 r8 3.9k c9 1uf d2 0.1 m f c31 c14 1000pf part # value rating tolerance r1 1meg 1/16 watt 5% r2 49.9k 1/16 watt 1% r3 1.2meg 1/16 watt 5% r4 2k 1/16 watt 5% r6 51k 1/16 watt 5% r7 30.1k 1/16 watt 5% r8 3.9k 1/4 watt 5% r9 249 1/16 watt 1% r10 604 1/16 watt 1% r11 5k 1/16 watt 5% r12 5k 1/16 watt 5% r13 10k 1/16 watt 5% r20 100k pot. q1 2n3906 30v q2 si3457dv 30v q3 irf7341 60v part # value rating tolerance c1 0.1uf 25v 20% c2 1.0uf 6v 20% c3 22nf 6v 5% c4 0.01uf 6v 5% c5 10uf 25v 20% c6 0.1uf 6v 20% c7 4.7uf 6v 20% c8 47nf 6v 5% c9 1.0uf 25v 10% c31 0.1uf 6v 20% d2 1n914 d3 1n914 d4 1n914 d5 1n914 d6 1n914 t1 20:20:2200 ame, inc. 8 ccfl backlight controller ame9001 overview the goal of the ame9001 application circuit is to drive a ccfl (cold cathode fluorescent lamp) with a high volt- age sine wave in order to produce an efficient and cost effective light source. the most common application for this will be as the backlight of either a notebook com- puter display, flat panel display, or personal digital assis- tant (pda). the ccfl tubes used in these applications are usu- ally glass rods about a foot long and 0.125-0.25 in diameter. typically they require a sine wave of 600v and they run at a current of several milliamperes. however, the starting (or striking) voltage can be as high as 2000v. at start up the tube looks like an open circuit, after the plasma has been created the impedance drops and cur- rent starts to flow. the iv characteristic of these tubes is highly non-linear. traditionally the high voltage required for ccfl opera- tion has been developed using some sort of transformer- lc tank circuit combination driven by several small power mosfets. the ame9001 application uses one external pmos, 2 external nmos and a high turns ratio trans- former with a centertapped primary. lamp dimming is achieved by turning the lamp on and off at a rate faster than the human eye can detect. these "on-off" cycles are known as dimming cycles. steady state circuit operation figure 1 (and 2) shows pmos q2 driving the center tap primary of t1. the gate drive of q2 is a pulse width modulated (pwm) signal that controls the current into the transformer primary and by extension, controls the current in the ccfl. the gate drive signal of q2 drives all the way up to the battery voltage and down to 7.5 volts below vbatt so that logic level transistors may be used without their gates being damaged. an internal clamp prevents the q2 gate drive (outa) from driving lower than vbatt-7.5v. nmos transistors q3-1 and q3-2 alternately connect the outside nodes of the transformer primary to vss. these transistors are driven by a 50% duty cycle square wave at one-half the frequency of the drive signal applied to the gate of q2. figure 3 illustrates some ideal gate drive waveforms for the ccfl application. figure 4 and 5 are detailed views of the power section from figures 1 and 2. figure 5 has the transformer parasitic elements added while figure 4 n application notes does not. referring to figures 4 and 5, nmos transis- tors q3-1 and q3-2 are driven out of phase with a 50% duty cycle signal as indicated by waveforms in figure 3. the frequency of the nmos drive signals will be the fre- quency at which the ccfl is driven. pmos transistor, q2, is driven with a pulse width modulated signal (pwm) at twice the frequency of the nmos drive signals. in other words, the pmos transistor is turned on and off once for every time each nmos transistor is on. in this case, when nmos transistor q3-1 and pmos transistor q2 are both on then nmos transistor q3-2 is off, the side of the primary coil connected to nmos transistor q3-1 is driven to ground and the centertap of the trans- former primary is driven to the battery voltage. the other side of the primary coil connected to nmos transistor q3-2 (now off) is driven to twice the battery voltage (because each winding of the primary has an equal num- ber of turns). current ramps up in the side of the primary connected to q3-1 (the on transistor), transferring power to the secondary coil of transformer. the energy transferred from the primary excites the tank circuit formed by the transformer leakage inductance and parasitic capaci- tances that exist at the transformer secondary. the para- sitic capacitances come from the capacitance of the trans- former secondary itself, wiring capacitances, as well as the parasitic capacitance of the ccfl. some applica- tions may actually add a small amount of parallel ca- pacitance (~10pf) on the output of the transformer in order to dominate the parasitic capacitive elements. when the pmos, q2, is turned off, the voltage of the transformer centertap returns to ground as does the drain of nmos transistor q3-2 (the drain of q3-2 was at twice the battery voltage). halfway through one cycle, nmos transistor q3-1 (that was on) turns off and nmos tran- sistor q3-2 (that was off) turns on. at this point, pmos transistor q2 turns on again, allowing current to ramp up in the side of the primary that previously had no current. energy in the primary winding is transferred to the sec- ondary winding and stored again in the leakage induc- tance l leak , but this time with the opposite polarity. the current alternately goes through one primary winding then the other. the duty cycle of pmos transistor q2 controls the amount of power transferred from the primary winding to the secondary winding in the transformer. note that the ccfl circuit can work with pmos transistor q2 on con- stantly (i.e. a duty cycle of 100%), although the power would be unregulated in this case. ame, inc. 9 ame9001 ccfl backlight controller figure 3. idealized gate drive waveforms figure 5. power stage single tube components with parasitic elements (same component designations used as for figures 1 and 2) figure 4. power stage single tube components (same component designations used as for figures 1 and 2) v batt 5v 0v 5v 0v v batt - 7.5v q2 gate q3-1 gate q3-2 gate (outa) (outapb) (outc) to control circuitry l leak l p l p 1:n q2 outa d = 0-100% vhi = vbatt vlo = vbatt-7.5v f = fosc q3-1 q3-2 ccfl t1 d5 d4 outapb d=50% vhi = 5v vlo = 0v f = fosc/2 outc d=50% vhi = 5v vlo = 0v f = fosc/2 signals outc and outapb are the inverse of each other. c parasitic v batt r9+r10 signals outc and outapb are the inverse of each other. v batt r9+r10 to control circuitry q3-1 t1 q2 q3-2 ccfl outc d=50% vhi = 5v vlo = 0v f = fosc/2 outa d = 0-100% vhi = vbatt vlo = vbatt-7.5v f = fosc outapb d=50% vhi = 5v vlo = 0v f = fosc/2 d4 d5 ame, inc. 10 ccfl backlight controller ame9001 figures 6,7 illustrates various oscilloscope waveforms generated by the ccfl circuit in operation. these fig- ures show that the duty cycle of the gate drive at q2 decreases as the battery voltage increases from 9 v to 21 v (as one would expect in order to maintain the same output power). the first three traces in figures 6 and 7 show the gate drive waveforms for transistors q2, q3-1, and q3-2, re- spectively. as mentioned before, the gate drive wave- form for transistor q2 drives up to the battery voltage but down only to approximately 7.5 v below the battery volt- age. the fourth trace (in figures 6,7) shows the voltage at centertap of the primary winding (it is also the drain of pmos transistor, q2). this waveform is essentially a ground to a battery voltage pulse of varying duty cycle. when the centertap of the primary is driven high, current increases through pmos transistor, q2 as indicated by the sixth trace down from the top. in region i the drain current of q2 is equal and opposite to the drain current of q3-1 since the gate of q3-1 is high and q3-1 is on. in region iii the drain current of q2 will be equal and oppo- site to the drain current of q3-2 (not shown). in region ii when pmos transistor q2 is switched off, the current through this transistor, after an initial sharp drop, ramps back down towards zero. in figures 6 and 7 the fifth trace down from the top shows the drain voltage of q3-1. (the trace for nmos transistor q3-2, not shown, would be identical, but shifted in time by half a period.) the seventh trace down from the top shows the current through the nmos transistor q3-1, which is equal to the current in pmos transistor q2 for the portion of time that pmos transistor q2 is conducting (see region i, for example). as the current ramps up in the primary winding, energy is transferred to the secondary winding and stored in the leakage induc- tance l leak (and any parasitic capacitance on the sec- ondary winding). if the current in the nmos transistor is close to zero when that nmos transistor is turned off that means that the ccfl circuit is being driven close to its resonant frequency. if the circuit is being driven too far from its resonant point then there will be large re- sidual currents in the transistors when they are turned off causing large ringing, lower efficiency and more stress on the components. so called "soft switching" is achieved when the mos drain current is zero while the mos is being turned off. the driving frequency and transformer parameters should be chosen so that soft switching oc- curs. once pmos transistor q2 completes one on/off cycle, it is repeated again with the alternate nmos transistor conducting. this complementary operation produces a symmetric, approximately sinusoidal waveform at the in- put to the ccfl load, as shown by the bottom trace in figures 6 and 7. the operation of the ccfl circuit can be divided into 4 regions (i, ii, iii, and iv) as shown in figures 6 and 7. figure 8-1 shows the equivalent transformer and load cir- cuit model for region i. during region i, one of the primary windings is connected across the battery, the current in that winding increases and energy is coupled across to the secondary. no current flows in the other winding be- cause its nmos is turned off and its body diode is re- verse biased. the drain of that nmos stays at twice the battery voltage because both primary windings have the same number of turns and the battery voltage is forced across the other primary winding. figure 8-2 shows the equivalent transformer and load circuit model for region ii. during region ii, the battery is disconnected from the primary winding. in this configura- tion, current flows through both of the primary windings. the current decreases very quickly at first then ramps down to zero at a rate that is slower than the current ramped up. the initial drop is due to the almost instanta- neous change in inductance when current flow shifts from one portion of the primary winding to both portions of the primary. figure 8-3 shows the equivalent transformer and load circuit model for region iii. during region iii, the primary winding opposite from the one used in region i is con- nected across the battery, increasing current in that pri- mary winding but in a direction opposite to that of region i. energy is coupled across to the secondary as in re- gion i but with opposite polarity. no current flows in the undriven winding because its nmos is turned off and its body diode is reverse biased. the drain of that nmos stays at twice the battery voltage because both primary windings have the same number of turns and the battery voltage is forced on the other primary. region iii is, effec- tively, the inverse of region i. figure 8-4 shows the equivalent transformer and load circuit model for region iv. during region iv, the battery is disconnected from the primary winding. in this con- figuration, current flows through both of the primary wind- ings with opposite polarity to that in region ii. the cur- rent decreases very quickly at first then ramps down to zero at a rate that is slower than the current ramped up. once again, the initial drop is due to the effective change in inductance when current flow shifts from one portion of the primary winding to both portions of the primary. re- gion iv is effectively the inverse of region ii. ame, inc. 11 ame9001 ccfl backlight controller figure 7. typical waveforms v batt =21v figure 6. typical waveforms v batt =9v region i region ii region iii region iv q2 gate q3-1 gate q3-2 gate center tap q3-1 drain i dq2 i dq3-1 i lamp v batt =9v 1.5v 5v 0v 5v 0v v batt 0v v batt x 2 0 0 i max 0 i max (outa) (outapb) (outc) (q2 drain) q3-1 gate q3-2 gate q3-1 drain region i region ii region iii region iv q2 gate i dq2 i dq3-1 i lamp 13.5v 0v 2 x v batt 0v 0a i max 0a i max 5v 0v 5v (outapb) (outc) center tap v batt 0v (q2 drain) v batt =21v (outa) ame, inc. 12 ccfl backlight controller ame9001 figure 8-1. region i figure 8-2. region ii figure 8-3. region iii figure 8-4. region iv figure 9. steady state dimming waveforms (1 st cycle not show) load i leak i c parasitic load i c parasitic i leak load i c parasitic i leak load i leak i c parasitic bright ct1 5v ssv ov ignore respond ignore respond always respond to over voltage faults ~ 6ms 5v ssc ov under voltage + under current faults over voltage faults tube current (time not to scale) 0.5v 3v 3v 3v ame, inc. 13 ame9001 ccfl backlight controller driving the ccfl unlike other conventional schemes for driving ccfls the secondary winding of the ame9001 method is not designed to look like a voltage source to the ccfl lamp. the circuit acts more like a current source (or a power source). the circuit will increase the duty cycle of q2 thereby dumping more and more energy across to the secondary tank circuit until the ccfl tube current achieves regulation or one of the various fault conditions is met. there is no special "striking period" as is neces- sary with some other schemes. when the circuit starts driving the transformer there is initially no arc struck in the ccfl. the ccfl load looks like an open circuit. the voltage across the ccfl will increase with each successive cycle. two events may then happen: 1) the gas inside the ccfl will ionize, the voltage across the ccfl will drop, the current through the ccfl will increase, and a stable steady state operating point will be reached. or.... 2) one of the three fault conditions will be met shutting down the circuit: a) the ccfl tube voltage continues to rise until the ovp pin is higher than 3.5v at which point the circuit will shut down. b) the ccfl voltage fails to rise high enough to keep the undervoltage portion of the ovp pin from trip- ping. c) the ccfl current fails to rise high enough to keep the undercurrent threshold at the csdet pin from tripping. note that condition a) can be met at any time while the ame9001 is enabled. condition b) and c) can only be met after the ssc pin has crossed 3v and four succes- sive undervoltage events occur in a row. the ssc pin is pulled to vss everytime the lamp is turned off, whether for a dimming cycle, user shutdown or fault occurrence. it ramps up slowly depending on the size of capacitor c3 connected to the ssc pin. the period of time when the b) and c) fault checks are disabled is called the "blank- ing" time. the blanking time occurs from the time ssc starts to ramp up until it reaches 3v. see figure 9 for some idealized waveforms illustrating the behavior just described. control algorithm there are 2 major control blocks (loops) within the ic. the first loop controls the duty cycle of the driving wave- form. it senses the ccfl current (figure 1 or 2, resistor r9 and r10) rectifies it, integrates it against an internal reference and adjusts the duty cycle to obtain the de- sired power. this loop uses error amplifier ea1 whose negative input is pin fb and whose output is comp. the positive input of ea1 is connected to a 2.5v reference. external components, r7 and c8, set the time constant of the integrator, ea1. in order to slow the response of the integrator increase the value of the product (r7 x c8). the second control block adjusts the brightness by turning the lamp on and off at varying duty cycles. each time the lamp turns on and off is referred to as a dim- ming cycle. at the end of each dimming cycle the ssv pin is pulled low, this forces comp low as well due to the clamping action of clamp1 shown in figure 1. at the beginning of a new dimming cycle comp tries to increase quickly but it is clamped to the voltage at the ssv(soft- start voltage) pin. a capacitor on the ssv pin (c8, fig- ure 1), which is discharged at the end of every dimming cycle, sets the slew rate of the voltage at the ssv pin, and hence also the maximum positive slew rate of the comp pin. [dimming cycle is explained more fully below] the bright and ct2 pins a user-provided voltage at the bright pin is compared with the ramp voltage at the ct1 pin (see figure 10). as the voltage at bright increases the duty cycle of the dimming cycle (and the brightness of the ccfl) increase. the frequency of the dimming cycles is set by the value of the capacitor at pin ct1 (c4 in figure 1 and 2) and it is also proportional to the current set by resistor r2. set- ting c4 equal to 0.01uf and r2 equal to 47.5k yields a dimming cycle frequency of approximately 125hz. the frequency should vary inversely with the value of c4 ac- cording to the relation: frequency(hz) = 1/[17 x r2 x c4] the brightness may also be controlled by using a vari- able resistor in place of r10 (see figure 11). in this case the bright pin should be pulled to vdd so that the ccfl remains on constantly. this method can lead to flicker at low intensities but it is easy to implement. harmonic distortion may also increase since the duty cycle of the waveform at the gate of q2 will vary greatly with brightness. when using burst brightness control the duty cycle of the driving waveforms should not vary because the ccfl is running at 100% power or it is turned off. as long as the battery voltage does not change the duty cycle of the driving waveform also does not change greatly. this means that harmonic distortion can be mini- mized by optimizing the frequency and transformer char- acteristics for a particular duty cycle rather than a large range of duty cycle. ame, inc. 14 ccfl backlight controller ame9001 figure 11. alternative brightness control figure 10. duty cycle dimming bright ct1 + - 3v + - 500mv s r q + - chop chop causes the ccfl to turn on and off periodically. c4 brightness control voltage inside chip outside chip 5v r 1 r 2 r 2r bright ct comp fb csdet rf + - 250mv inside chip outside chip this method disables duty cycle dimming maximum current= k r 1 //(2r+r) minimum current= k (r 1 +r 2 )//(2r+r) 2.5v t1 + - chop + - always hi to pwm comparator to fault control logic ame, inc. 15 ame9001 ccfl backlight controller rt2, rdelta pin the frequency of the drive signal at the gate of q2 is determined by the vco shown in figure1. a detail of the vco is shown in figure 12. the user sets the minimum oscillator frequency with the resistor connected to pin rt2 (r2 in the figures). the relation is: frequency (hz) = 2.8e9 / r2 (ohms) you can see from the formula that as r2 is increased the frequency gets smaller. all other things being equal, as the battery voltage in- creases the duty cycle of the driving waveform at the gate of q2 decreases. often the waveform becomes less sinusoidal as the duty cycle decreases. to avoid this unwanted effect and to ensure that the fets remain in a "soft switching mode" the application described here adjusts the oscillator frequency upwards as the battery voltage increases. an increase in driving frequency is desirable to minimize harmonic distortion of the output waveform as the duty cycle of the drive signal at the gate of q2 decreases. resistor r3 controls how much the oscillator frequency increases as a function of battery voltage. the relationship is: delta frequency (hz) = 3.44e8 * (vbatt -1.25) / r3 you can see from the formula that the frequency will increase as the battery voltage increases. the amount of this increase is set by r3. in the current application ea2 (figure 1) is connected in unity gain which will pro- vide a constant 1.25v at the cscomp pin and subse- quently at the vco_control and rdelta input of the vco. even though vco_control is a fixed voltage the frequency of the vco still modulates because the current through r3 changes as the battery voltage increases and hence increases the charging current into the timing capacitor of figure 12 thereby increasing the oscillator frequency. supply voltage pins, vdd and pnp most of the circuitry of the ame9001 works at 5v with the exception of one output driver. that driver (outa) and its power pad (vbatt) must operate up to 24v al- though the outa pad may never be forced lower than 8 volts away from the vbatt pin. the outa pin is inter- nally clamped to approximately 7.5 volts below the vbatt pin. the ame9001 uses an external pnp device to provide a regulated 5v supply from the battery voltage (see fig- ure 13). the battery voltage can range from 7v< vbatt < 24v. the pnp pin drives the base of the external pnp device, q1. the vdd pin is the 5v supply into the chip. a 4.7uf capacitor, c7, bypasses the 5v supply to ground. if an external 5v supply is available then the external pnp would not be necessary and the pnp pin should float. when the ce pin is low (<0.4v) the chip goes into a zero current state. the chip puts the pnp pin into a high impedance state which shuts off q1 and lets the 5v sup- ply collapse to zero volts. when low, the ce pin also immediately turns pmos transistor q2 off, however tran- sistors q3-1 and q3-2 will continue to switch until the 5v has collapsed to 3.5v. allowing the q3 transistors to continue to switch for some time after q2 is turned off permits the energy in the tank circuit to be dissipated gradually without any large voltage spikes. the vdd voltage is sensed internally so that the switch- ing circuitry will not turn on unless the vdd voltage is larger than 4.5v and the internal reference is valid. once the 4.5v threshold has been reached the switching cir- cuitry will run until vdd is less than 3.5v (as mentioned before). output drivers (outa, outapb, outc) the outapb and outc pins are standard 5v cmos driver outputs (with some added circuitry to prevent shoot through current). the outa driver is quite different (see figure 14). the outa driver pulls up to vbatt (max 24v) and pulls down to about 7.5 volts below vbatt. it is internally clamped to within 7.5v of vbatt. on each transition the outa pad will sink/source about 500ma for 100ns. after the initial 100ns burst of current the current is scaled back to 1ma(sinking) and 12ma(sourcing). this technique allows for fast edge tran- sitions yet low overall power dissipation. fault protection, the ovp and csdet pins the ame9001 checks for 3 different fault conditions. when any one of the fault conditions is met then the circuit is latched off. only a power on reset or toggling the ce pin will restore the circuit to normal operation. (see figure 15 for a schematic of the fault circuitry.) the first fault condition check can be used to detect overvoltages at the ccfl. specifically, if the ovp pin is above 3v then this fault condition is detected. the first fault condition is always enabled, thus there is no blank- ing period, or 4 succesive faults required for shutdown. the second fault condition check can be used to en- sure that the ccfl voltage is above some certain voltage ame, inc. 16 ccfl backlight controller ame9001 level on a cycle by cycle basis. if the ovp pin does not cross its 250mv threshold once during four successive clock periods in a row then this fault will be triggered. this protection is disabled while the ssc ramp is below 3v such as during the initial start up and at the beginning of every dimming cycle. the 1 st ssc ramp after power on reset (or ce enabled) is 150 times slower than sub- sequent start up ramps. this slow first ramp allows more time for a cold tube to strike before the chip senses a fault and shuts down. in order to enable the first two fault condition checks then the ovp pin must, indirectly, sense the high volt- age at the input of the ccfl. the actual ccfl voltage must be reduced by using either a resistor or capacitor divider such that in normal operation the voltage at ovp is higher than 250mv but lower than 3v. the third fault condition check can be used to monitor the ccfl current. specifically, it checks whether the voltage at the csdet pin is higher than 250mv. if csdet does not cross its 250mv threshold once during 4 suc- cessive clock cycles then this fault will be triggered. this protection is disabled while the ssc ramp is below 3v, such as during the initial start period, and at the begin- ning of every subsequent dimming cycle. this fault con- dition is used to check that a reasonable minimum amount of current is flowing in the tube. please note that the application circuit of figure 2 uses a resistor divider to drive the ovp pin to a voltage above 250mv but below 3v. that effectively disables the first two fault condition checks. some applications may not require all 3 fault condition checks. the third fault condi- tion is usually sufficient to detect open circuit faults. figure 15 is a simplified schematic of the fault protec- tion circuitry used in the ame9001. most of the signals have been previously defined however some need a little explanation. the vddok signal is a power ok signal that goes high when the 5v supply (vdd) is valid. the chop signal stops the operation of the switching cir- cuitry once every dimming cycle for burst mode bright- ness control. the output signal, first, is high during the first burst cycle after power is turned on. it causes the ssc pin to source 150 time less current than on subsequent dimming cycles. the norm signal is an enable signal to the switching circuitry. when it is high the circuit works normally. when it is low the switching circuitry stops. ssc and ssv pins the ssc pins primary role is to define a time period in which the 2nd and 3rd fault condition (previously de- scribed) are disabled. this period of time is called the blanking interval. during the initial start up period after a power on reset or just after a low to high transition on the ce pin the ssc pin sources 1ua into an external capacitor(c3). the voltage on ssc ramps upwards to- wards vdd. the blanking interval is defined as the time during which v(ssc) < 3v. once the voltage at ssc crosses 3v the blanking interval is finished and all three fault condition checks are enabled. at the beginning of the next dimming cycle the ssc pin is pulled to vss then allowed to ramp upwards again, however during all subsequent dimming cycles the ssc pin sources 150ua instead of 1ua as was the case of the first cycle. in effect, the two different sourcing currents means that the first blanking interval is 150 times as long as all sub- sequent blanking intervals. this allows a cold tube more time to strike before shutting down due to an undercur- rent or undervoltage fault. (please see figure 9 for further clarification of the blanking function.) the ssv pin (like the ssc pin) is pulled to ground at the beginning of every dimming cycle then sources 20ua into an external capacitor. this creates a 0 to 5 volt ramp at the ssv pin. this ramp is used to limit the duty cycle of the pwm gate drive signal available at the outa pin. the ssv pin accomplishes duty cycle limiting by clamping the comp voltage to no higher than the ssv voltage. because the magnitude of the comp voltage is proportional to the duty cycle of the pwm signal at outa the duty cycle starts each dimming cycle at zero and slowly increases to its steady state value as the voltage at ssv increases. (figure 9 shows this opera- tion.) this type of duty cycle limiting is commonly called soft-start operation. soft start operation lessens over- shoot on start up because the power increases gradually rather than immediately. unlike the ssc pin the current sourced by the ssv pin remains approximately 20ua during all dimming cycles. ringing due to the leakage inductances of transformer t1 volt- ages at the drains of q3 can potentially ring to values substantially higher than the ideal value (which is twice the battery voltage). the application schematic in figure 2 uses a snubbing circuit to limit the extent of the ringing voltage. components c9,r8,d2 and d3 make up the snubbing circuit. the nominal voltage at the common ame, inc. 17 ame9001 ccfl backlight controller node is approximately twice the battery voltage. if either of the drains of q3 ring above that voltage then diodes d2 or d3 forward bias and allow the ringing energy to charge capacitor c9. resistor r8 bleeds off the extra ringing energy preventing the voltage at the common node from increasing substantially higher than twice the battery voltage. the extra power dissipation is: p(dissipated) = vbatt 2 / r8 for the example, in figure 2, the power dissipation of the snubber circuit with vbatt=15v is 58mw or approxi- mately 1% of the total input power. the value of r8 can be optimized for a particular application in order to mini- mize dissipated power. excessive ringing is usually a sign that the driving fre- quency is not well matched to the resonant characteris- tics of the tank circuit. in a well designed application a snubber circuit will not be necessary. layout considerations due to the switching nature of this circuit and the high voltages that it produces this application can be sensi- tive to board parasitics. in fact, one of the advantages, of this design is that the circuit uses the parasitic elements of the application as resonant components, thus elimi- nating the need for more added components. particular care must be taken with the different gounding loops. the best performance has been obtained by us- ing a star ground technique. the star technique re- turns all significant ground paths back to the center of the star. ideally we would place the center of the star directly on the vss pin of the ame9001. the bypass capacitors would, ideally, be connected as close to the center of the star as possible. the schematic in figure 2 attemps to show this star ground configuration by bring- ing all the ground returns back to the same point on the drawing. separate ground returns back to the star are especially important for higher current switching paths. ame, inc. 18 ccfl backlight controller ame9001 figure 12. vco detail figure 13. ldo detail 1 - 2 + - start up inside chip outside chip pnp vdd ce v ddok en 2.5v 4.7 m m m m f 27 < v batt < 24 v batt r4 q1 to fault logic c7 to user enable circuitry 1.5v vss 3.0v i_in 0 i_out 0 50:1 curent divider clk ramp + - + - vco_control rt2 inside chip outside chip 1.25v cscomp cs rdelta r3 r2 v batt ame, inc. 19 ame9001 ccfl backlight controller figure 14. outa driver circuitry figure 15. fault logic pwm signal external pmos, q2 outa vbatt 100ns 100ns 1ma inside chip outside chip bv=7.5v bv=4v bv=5v 250mv 3.3v + - + - + - resb q clk 2 bit counter resb q clk 2 bit counter q q set clr s r q q set clr s r blank first norm + - 3.3v ovp csdet ssc bright ct1 clk ce v ddok v dd 3v chop all inside the chip ame, inc. 20 ccfl backlight controller ame9001 application component description figure 2 shows one typical application circuit for single tube drive. figure 16 shows a similar application circuit that is optimized for 4 tube operation. similar compo- nent designations are used on similar components both in figure 2 and figure 16 as well as throughout this appli- cation note. r1 - weak pull up for the chip enable (ce) pin. the voltage at ce will normally rise to 5 volts for a 12v supply. pull down on the ce node to disable the chip and put it into a zero idd mode. if the user wishes to drive node ce with 3.3 or 5.5 volt logic then r1 is not necessary c1 - this capacitor acts to de-bounce the ce pin and to slow the turn on time when using r1 to pull up ce. this can be useful when the battery power is discon- nected from the circuit in order to turn the circuit off, when the battery is reconnected the chip does not immediately turn on which allows the battery voltage to stabilize before switching starts. if the user is ac- tively driving the ce pin then the c1 capacitor may not be necessary. r3 - this resistor connected to the rdelta pin deter- mines how much the oscillator frequency will change with battery voltage. the relation, which is found ear- lier in the text, is: delta frequency (hz) = 3.44e8 * (vbatt-1.25) / r3 c2 - this 1uf capacitor bypasses and stabilizes the internal reference c3 - this capacitor determines the length of the blank- ing interval at the beginning of every dimming cycle and when the chip is first powered on. at the end of every dimming cycle this capacitor is discharged to vss then allowed to charge up at a rate controlled by its internal current source and c3. when the voltage on c3 (pin ssc) crosses 3 volts the blanking interval is over and all fault checks are enabled. the charging current into c3 (out of pin ssc) is normally 150ua but for the very first cycle after the chip is enabled the current is only 1ua. so the blanking interval for the first cycle is: t(seconds) =( c3) * (3volts) / (1e-6amps) and for subsequent dimming cycles the blanking in- terval is: t(seconds) = (c3) * (3volts) / (150e-6amps) c31 - this capacitor is used to prevent chatter on the faultb pin during start up r2 - r2 sets the frequency of the oscillator that drives the fets. the relation between r2 and frequency, that was found previously in the text, is: frequency (hz) = 2.8e9/r2 r2 = 56k yields approximately 50khz note: that this is the frequency of the nmos(q3) gate drive. the pmos(q2) gate drive is exactly twice this value. c30 - this capacitor filters signals feeding the ovp pin. by increasing c30 the user makes the circuit less sensitive to fast overvoltage conditions. r4 - this resistors pulls the base of q1 up to vbatt. coupled with q1 and c7 it is part of the 5v regulator that supplies the working power to the ame9001. when the pnp pin is turned off the base of q1 is pulled high through r4, turning off q1 and allowing the voltage at the vdd node (vsupply) to decay towards zero. q1 - this common pnp transistor (2n3906 is ad- equate) forms part of the 5v linear regulator which supplies power to most of the ame9001. r6 - this resistor, together with adjustable resistor r20, form a resistor divider that divides the regulated 5v down to some lower voltage. that lower voltage is used to drive the bright pin which, in turn, deter- mines the duty cycle of the the dimming cycles and therefore the brightness of the lamps. if the user is driving the bright pin with his/her own voltage source then r6 and r20 are not necessary. c6 - this capacitor bypasses the bright pin. a noisy bright pin can cause unwanted flicker. ame, inc. 21 ame9001 ccfl backlight controller r20 - see description of r6 c14 - this capacitor sets the slope of the soft-start ramp on pin ssv. the voltage at ssv limits the duty cycle of the q2 gate drive signal available at pin outa. the voltage at the comp node is internally clamped to the ssv node. therefore the c14 cap limits how fast ssv, and hence, comp can increase. the charg- ing current out of ssv is approximately 20ua so the rate of change of the ssv voltage is: ssv(volts/sec) = (20e-6amps) / c14 c5 - this is the main battery bypass capacitor. c4 - this capacitor sets the frequency of the dimming cycles according to the relation: dim cycle freq(hz) = 1 / [(17) * (r2) * (c4)] note that the frequency is also a function of r2. so the frequency of the main oscillator and the frequency of the dimming oscillator are not independent. c7 - this capacitor is the load capacitor for the 5v linear regulator. as such it also bypasses the 5v sup- ply and should be laid out as close to the ame9001 as possible. c8 - this capacitor, in combination with resistor r7, determines the time constant for the error amplifier (integrator) ea1. the integrator is the primary loop stabilizing element of the circuit. in general this appli- cation is tolerant of a large range of integrator time constants. increase the (c8 x r7) product to slow down the loop response. r7 - see c8 d6 - this diode can catch any negative going spikes on the drain of q2. this diode is not strictly neces- sary. this is not a freewheeling diode such as in a buck regulator. since the primary windings are tightly coupled to each other the body diodes of q3-1 and q3-2 keep their own drains clamped to vss as well as the drain of q2. the spikes that diode d6 may catch are of short duration and small energy. q2 - this is a pmos device. by modulating its gate drive duty cycle the power into the transformer, and then into the load, can be controlled. the breakdown of this device must be higher than the highest battery voltage that the application will use. the peak current load is roughly twice the average current load. q3-1, q3-2 - these are nmos devices. they are driven alternately with 50% duty cycle gate drive. the frequency of the gate drive is one half of the gate drive frequency of q2. the gate drive is from 0 to 5 volts. the breakdown voltage of these devices must be at least twice the highest battery voltage. peak current is roughly twice the average supply current. c9,r8,d2,d3 - these devices form a snubber circuit that can dissipate ringing energy. the snubber circuit is not strictly necessary. in fact a well designed cir- cuit should not require these devices. (these elements were described in more detail earlier.) r9, r10 - the sum of r9 and r10 sets the current in one ccfl tube. as the sum of r9 and r10 decreases the tube current goes up, as the sum of r9 and r10 increase the tube current goes down. the rms tube current is roughly: irms = 6v / (r9 + r10) r9 and r10 also form a voltage divider that drives the csdet pin. the purpose of the voltage divider is to keep the maximum voltage at csdet under 5 volts under all conditions. the csdet pin checks to see if there is any current in the ccfl. if the voltage at csdet is larger than 250mv once every clock cycle then the ame9001 assumes there is current in the ccfl and allows operation to continue. d4,d5 - these diodes rectify the current through the ccfl to provide a positive voltage for regulation by the error amplifier, ea1. the following components are only used for multiple tube operation: q4,q5 - these bipolar devices buffer the gate of q2. that allows q2 to be made much bigger without dissi- pating more power or increasing the cost of the ame9001. q4 is an npn transistor and q5 is a pnp transistor. r35,r36,d16 - these devices form a voltage divider and rectifier combination to sense higher than normal ame, inc. 22 ccfl backlight controller ame9001 transformer operating voltages. ( this operation is ex- plained in more detail below.) r38,r39,d17 - see r35,r36,d16 description above. you can diode "or" as many of these divider/rectifier circuits as you have different transformers. each time you add another double output transformer you must add another set of these resistors and diode networks. ( this operation is explained in more detail in the next section.) multiple tube operation the ame9001 is particularly well suited for multiple tube applications. figure17 shows the power section of a two tube application. the major difference between this application and the single tube application is the ad- dition of another secondary winding on the transformer. the primary side of the transformer and its associated fets are exactly the same as the single tube case al- though the fets may need to be resized due to the in- creased current in two tube applications. the secondaries are wound so that the outputs to the ccfl are of opposite phase (see figure 18). when the voltage at one secondary output is high (+600 volts) the other secondary output should be low (-600 volts). the other secondary terminals are connected to each other. in a balanced circuit the voltage at the connection of the two secondaries will, ideally, be zero. of course in a real application the voltage at the connection of the two sec- ondaries will deviate somewhat from zero. the common connection of the secondaries offers us an excellent method to check for high voltage fault condi- tions. as previously mentioned, when the ccfl loads are balanced then the voltage at the common connection of the secondaries will remain relatively low compared to the high voltages available at the other terminals of the secondaries. however, when the loads become unbal- anced, as would be the case if a tube was broken or there was a bad connection, then the voltage at the com- mon point of the secondaries will be much higher than its normal value. it is simple to size resistors r35 and r36 in figure17 such that in normal operation the ovp volt- age remains below 3 volts while during abnormal opera- tion the ovp voltage goes above 3 volts causing a sys- tem fault. the multi-tube configuration is modular. since each double transformer can drive two ccfls it is possible to construct 2, 4, 6..... tube solutions using the basic archi- tecture. of course the fets must be properly sized to handle the increased current. figure19 shows a 4 tube application. in this configuration the common secondary connection (the node not connected to the lamp) is made with the opposite transformer. in this way the sec- ondary current from the winding on the first transformer should be equal to the secondary current of its compan- ion winding on the second transformer. in the case of 4 lamps driven by two transformers there are two sets of common secondary nodes. each set drives a resistor divider ( in this case r35/r36 and r38/r39) whose out- puts are diode "or'd" together at the ovp node. that way either transformer that experiences an overvoltage fault condition will be able to pull up the ovp node and cause the system to shut down. the concept can be expanded for more than four tubes. for every 2 extra tubes that need to be added the user must add one more transformer, a resistor divider, and a small diode such as a 1n914. figure 16 shows a complete multi-tube architecture schematic. analogous components have been given the same numbers as in the single tube schematic. there is really very little difference between the the single tube configuration and the multi-tube version. transistors q4 and q5 are added to buffer the high side drive outa. this may be necessary because the pmos devices for larger current applications have larger gate drive require- ments. capacitor c30 is added to the ovp node so that unwanted high frequency signals do not couple to the ovp node and cause an undesired shutdown. the mos transistors are sized bigger for the 4 tube application as would be expected. the peak currents are much higher so the vbatt bypassing capacitor must be increased as well. the schematic shows c5 as a 100uf capacitor but higher values such as 220uf are not uncommon in order to minimize ripple on vbatt. ame, inc. 23 ame9001 ccfl backlight controller figure 16. four tube application schematic c7 4.7uf c4 0.01uf c8 47nf r7 30.1k c3 0.022uf c6 0.1uf r2 49.9k vref 1 ce 2 ssc 3 rdelta 4 faultb 5 rt2 6 vss 7 ovp 8 cs 9 cscomp 10 csdet 11 cspeak 12 outc 13 outapb 14 outa 15 vbatt 16 duty 17 vsupply 18 ct1 19 fb 20 comp 21 bright 22 ssv 23 pnp 24 ame9001 u1 c1 0.1u c14 1000p + c5 100uf vref d6 1n5819 vdd r20 100k q1 r4 2k 1 3 2, 4 q2 5602 lx r3 1.2meg q5 pnp q4 npn 2n3906 2n3904 2n3906 pnp c30 100p c2 1uf r6 51k c31 0.1uf d4 in914 r10 852 q3-1 q3-2 irfr3303 irfr3303 r8 3.9k c9 1uf d2 in914 snub d3 in914 2 12 5 7 10 3 9 4 t1 2xtrans 2 12 5 7 10 3 9 4 t2 2xtrans r35 r36 d16 in914 400k 3k r9 303 ovp d17 in914 r38 r39 400k 3k out-1 d5 in914 r1 1meg batt ce bright ame, inc. 24 ccfl backlight controller ame9001 figure 17. double ccfl power section figure 18. double transformer construction detail low voltages in the center large positive (negative) voltage large negative (positive) voltage secondary secondary primaries common core low voltages ea1 q3-1 q2 r10 r7 2.5v c8 r9 q3-2 v batt t1 d4 d5 ovp r35 r36 outa outb outc outside chip inside chip fb comp 250mv csdet to pwm comparator to fault logic ame, inc. 25 ame9001 ccfl backlight controller figure 19. four tube power section d4 d5 q3-2 q3-1 q2 to r7 and c8 integrator r35 r36 to ovp t1 t2 v batt r38 r39 r10 r9 outa outapb outc to csdet ame, inc. 26 ccfl backlight controller ame9001 n package dimension qsop24 min max min max a 1.524 1.752 0.060 0.069 a1 0.101 0.228 0.004 0.009 a2 b 0.203 0.304 0.008 0.012 b1 0.203 0.279 0.008 0.011 c 0.177 0.254 0.007 0.010 c1 0.177 0.228 0.007 0.009 d 8.559 8.737 0.337 0.344 zd e 5.791 6.197 0.228 0.244 e1 3.810 3.987 0.150 0.157 l 0.406 1.270 0.016 0.050 l1 e j k 0 o 8 o 0 o 8 o 1 5 o 15 o 5 o 15 o 2 0 o - 0 o - r 1.27ref 0.050ref symbols millimeters inches 1.473ref 0.058ref 0.838ref 0.033ref 0.254bsc 0.010bsc 0.635bsc 0.025bsc 1.27ref 0.050ref 0.33 x 45 o 0.013 x 45 o top view bottom view side view end view detail a d e1 e k j see detail a b e zd a a2 a1 c1 b1 (c) (b) c l1 l c c 1 c 2 r life support policy: these products of ame, inc. are not authorized for use as critical components in life-support devices or systems, without the express written approval of the president of ame, inc. ame, inc. reserves the right to make changes in the circuitry and specifications of its devices and advises its customers to obtain the latest version of relevant information. ? ame, inc. , september 2003 document: 2006-ds8803/8814-g e-mail:longman@rccn.com.cn address:room 2101, no.2 building yulan garden, no.50 puhuitang rd,shanghai,prc zip:200030 tel : 86-21-64285731/32 ext:8033 sales manager:longman xu fax: 86-21-64393342 |
Price & Availability of AME9001AETH
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |